1. Field of the Invention
The present invention relates to a data processor wherein execution of instructions is controlled by a microprogram, and to be further detailed, relates to a data processor which processes a set of instructions wherein one instruction has various formats.
2. Description of Related Art
In the conventional data processors, the data processor is known which is constituted in a manner that a specific bit field (hereinafter referred to as parameter) is cut out from an instruction code to specify an operand size, an ALU operation or the like, and this parameter is given to an instruction execution unit to execute the instruction. As an example of such a data Processor, description is made hereinafter and with reference to U.S. Pat. No. 4,312,034.
First, FIG. 1 is a block diagram showing a configuration of the above-described conventional data processor.
In FIG. 1, numeral 71 designates an instruction register, which latches an instruction code to be executed next. Numeral 72 designates an instruction decoder, which is concretely constituted with a PLA (Programmable Logic Array). This instruction decoder 72 decodes an instruction given from the instruction register 71, and outputs a micro entry address. Numeral 73 designates a micro entry address latch, which latches the micro entry address given from the instruction decoder 72. Numeral 74 designates a micro ROM which outputs a micro-instruction designated by the micro entry address given from the micro entry address latch 73. Numeral 75 designates an micro-instruction register, which latches the micro-instruction outputted from the micro ROM 74. Numeral 76 designates a parameter latch, which latches a bit field as a parameter cut out from the instruction code latched in the instruction register. Numeral 77 designates a multiplexer, which selects either of the outputs of the microinstruction register 75 and the parameter latch 76. Numeral 78 designates an ALU, which executes an ALU operation according to the output of the multiplexer 77. Numeral 79 designates a data operation unit constituted with the multiplexer 77 and the ALU 78.
The operation of such a conventional data processor is as follows.
When an instruction using the ALU such as addition, subtraction, logical product, logical sum, exclusive-or or the like is outputted from the instruction register 71, the instruction is decoded by the instruction decoder 72, and an entry address of a micro-program used for executing the operation is latched in the micro entry address latch 73. The micro-instruction designated by the micro entry address which is kept latched in the micro entry address latch 73 is read from the micro ROM 74, being latched in the micro instruction register 75.
On the other hand, a parameter required for the actual ALU operation is cut out from the instruction code latched in the instruction register 71, and is latched in the parameter latch 76. Information obtained by multiplexing the field designating ALU operation among information latched in the micro-instruction register 75 and the information latched in the parameter latch 76 by the multiplexer 77 is given to the ALU 78, and based on this information, a concrete ALU operation is performed in the data operation unit 79.
Thus, the size of the micro ROM is curtailed by adopting a configuration capable of processing instructions such that different ALU operations are to be executed by the same micro-instruction.
Since the conventional data processor is constituted as described above, in the case where a set of instructions is processed wherein one instruction has various formats, bit allocation differs depending on each instruction format even for the same instruction, and therefore the parameter to be cut out differs. Accordingly, it is required to set in advance the entry address of the micro-program on a format basis, and therefore a problem exists that the size of the micro ROM is enlarged.